The present disclosure generally relates to a data processing system and, more particularly, relates to memory transaction prioritization in a data processing system.
In a computer processing system, memory requirements may be driven by the performance of a workload on the system. A host bus protocol of the system's processor ensures performance, for example, by maintaining latency and throughput across different reads and writes to the memory. An efficient and well-designed cache structure provides faster turnaround time in fetching data that is being shared across cores of a processor to make up for inherent gaps in fetching streams from the memory.
A memory buffer also plays a role in increasing throughput and optimizing the memory usage patterns with dual in-line memory modules. However, during heavy utilization and targeted memory usage, a memory controller of the processing system can stall. When this happens, the memory controller may retry some transactions due to the memory being busy and/or may retry some of the reads/writes while some of the internal logic and queues are full.